Clock and Data Recovery (CDR) circuits form a part of Serializer/Deserializer (SerDes) receivers. The CDR circuits track the phase of a sampling clock based on some criterion, such as minimizing a Mean-Squared-Error (MSE). Conventional CDR circuits are commonly designed to achieve low target bit-error-ratios (BER) on the order of 10−12 to 10−15 errors per bit. One category of CDR circuits commonly used is bang-bang CDR. Bang-bang CDR is widely used in SerDes circuits due to superior jitter tolerance and insensitivity to the Nyquist data pattern (i.e., 1010 . . . ).
When bang-bang CDR and a decision feedback equalizer (DFE) are implemented together in a receiver, coupling between bang-bang timing loops and the DFE can occur. Due to the coupling, the point at which bang-bang CDR will settle moves to the left of the pulse response (or the left of center with respect to a slicer input eye). The coupling between bang-bang timing loops and the DFE feedback can cause the sampling phase to continue moving further to the left, creating a snowball effect that can result in error propagation. The jitter tolerance of bang-bang CDR is reduced since the sampling phase is no longer at the center of the eye.
It would be desirable to have a method and/or apparatus to eliminate coupling between bang-bang CDR and DFE when implemented together.